Agentic Chip Factory

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Agentic Chip Factory

Describe the chip you want to build. The LLM will guide workload → constraints → stack → Pareto → CHIPS.md.

stage: workloadType / for rvstack commands. Catalog and manuals add stable prompt tokens.

SiFive Chip Catalog

Solution templates

AI & ML70B dense LLM inference · 120 kW

Matrix/vector acceleration with software-compatible differentiation for LLM and vision workloads.

Data Centercloud AI training and inference offload · 180 kW

High-performance host cores, Intelligence accelerators, coherent fabrics, open-source SW.

Edge Computing8B edge LLM · 35 W

Power-efficient Essential + Intelligence lanes, compact memory, secure telemetry.

AutomotiveADAS + zonal control · 60 W

Functional safety-oriented compute with redundancy and qualification evidence.

StorageNVMe / object store controllers · 80 W

Controllers with inline accelerators and predictable performance under sustained IO.

Aerospace & Defensemission compute / radiation-aware · mission-defined

High-reliability compute with trace, RAS, and qualification evidence.

Intelligence Series

AI matrix, vector, and accelerator-control cores

XM Gen 2 — LLM matrix tile
matrix engine
X300 core
X300 core
X300 core
X300 core
memory
X300 / X390 — ACU + vector control
front end
vector engine
scalar execution
memory
VCIX
SSCI
IO
X200 — Vector edge AI
front end
vector
scalar
memory
VCIX
SSCI
IO
X100 — Compact edge AI
front end
vector
scalar
memory
VCIX
SSCI
security

Performance Series

P400, P500 Gen 3, P600, P800 application cores

P870-D — Datacenter host cluster
PM
trace
CLINT
APLIC
WorldGuard
front end
vector
scalar execution
L2 / memory
CHI.E
IOMMU
P870-D cluster
P800 — High-performance app core
P670 — Balanced app core
front end
4-issue OoO
2×128b vector
private L2
system IP
AIA / MSI
WorldGuard
up to 16 cores
shared L3 / coherent fabric
P570 Gen 3 — Compact perf core
P550 Gen 3 — Mid-range perf core
front end
3-issue Gen3 OoO
cache stashing
private L2
system IP
AIA / MSI
WorldGuard
multi-core clusters
shared L3
P450 — Entry perf core

Essential Series

E/S/U control cores for MCU, RTOS, embedded Linux

E7 — Embedded control
front end
dual-issue scalar
L1 / TIM
shared L2
AIA / MSI
WorldGuard
core local
front port
RTOS
debug / trace
S7 — Safety-critical control
front end
dual-issue scalar
L1 / TIM
shared L2
AIA / MSI
WorldGuard
core local
front port
RTOS
debug / trace
U7 — Embedded Linux
front end
dual-issue scalar
L1 / TIM
shared L2
AIA / MSI
WorldGuard
core local
front port
MMU / Linux
hypervisor
E6 — MCU
S6 — RTOS control
U6 — Linux capable

Automotive Series

Safety-oriented compute lanes

S7-A — Auto safety control
ASIL D
ISO 26262
trace
front end
dual-issue RV64
split-lock
WorldGuard
ECC / RAS
L1 / L2 memory
debug
core local port
front port / AMBA
E7-A — Auto MCU
front end
dual-issue scalar
L1 / TIM
shared L2
AIA / MSI
WorldGuard
core local
front port
RTOS
debug / trace
E6-A — Auto entry MCU

RVstack — skills & MCP

Specialist skills routed by the ACF console model. Click to insert into the active session.

/rv-architecturearch
Core/SoC concepts: Rocket, BOOM, CVA6, caches, TileLink/AXI, accelerators, memory maps, PPA.
/rv-rtlmodel
Parameterized RTL/Chisel, generator integration, lint, CDC, synthesis hygiene.
/rv-dvmodel
DV plan, directed tests, random/regression, assertions, formal, coverage closure.
/rv-emulationemu
Verilator/VCS, FireSim/FPGA, trace capture, workload replay, perf counters.
/rv-toolchainsw
GCC/LLVM/binutils/newlib/glibc, ISA flags, linker scripts, bare-metal tests.
/rv-linux-bootsw
Boot ROM, OpenSBI, U-Boot, device tree, kernel config, rootfs, drivers.
/rv-qualificationsw
Reliability, characterization, production test, binning, yield data.
/rv-pnrpnr
Synthesis, DFT, floorplan, placement, CTS, routing, STA, power, IR/EM, DRC/LVS.
/rv-tapeouttapeout
Freeze RTL/netlist/GDS, signoff evidence, DFT, package/test, fab docs, errata.