ACF onboarding ?

Introduction

approval gated ?

New user guide ?

Use ACF as a requirements-to-evidence cockpit

Agentic Chip Factory starts with product intent, converts it into CHIPS.md, lets the team pick chip families and interconnect assumptions, then routes approved work through reproducible CLI and Web TUI execution.

First path through the demo ?
  1. Start with intent
  2. Compose CHIPS.md
  3. Select chip lanes
  4. Model PPA
  5. Review topology
  6. Execute through Web TUI

Flow intro ?

Step-by-step ACF flow

1. Start with intent?

Describe the product, workload, deployment, and business objective in the Design Dialog.

2. Compose CHIPS.md?

ACF turns the dialog into a structured contract with product target, selected stack, constraints, execution plan, and approval policy.

3. Select chip lanes?

Use Design Stack to pick SiFive series, exact chips, generator lanes, software enablement, and validation paths.

4. Model PPA?

Adjust power, area, latency, throughput, memory, and matrix assumptions in Spec Envelope.

5. Review topology?

Use Chips View to inspect multi-core, peer-chip, IO, and rack interconnect assumptions.

6. Execute through Web TUI?

After approval, use the browser CLI to run ACF commands, rvstack skills, and backend workflow turns.

CHIPS.md ?

How to compose the executable design contract

CHIPS.md should be short enough to review and specific enough to execute. Treat it as the contract between product intent, chip stack selection, constraints, interfaces, and approval policy.

Start in Design Dialog, confirm the stack in Design Stack, tune Spec Envelope, then approve only when the generated CHIPS.md matches the intended design decision.

Product Target ?

Name, workload, deployment, optimization priority, and natural-language intent.

Selected RISC-V Stack ?

SiFive cores, generator lanes, software paths, verification lanes, and chip roles.

Constraints ?

Power, area, latency, throughput, matrix policy, memory plan, and software plan.

Execution Plan ?

Specs, PPA, Chipyard/RTL, toolchain, DV, emulation, validation, qualification, and handoff.

Approval Policy ?

Explicit gates for CHIPS.md creation, proprietary IP access, custom ISA acceptance, PPA escalation, export, and fab handoff.

rvstack skills ?

Skills powering the Web TUI command line

4 shown
plan/rv-plan ?

Plan a RISC-V design stack and execution path from CHIPS.md.

rtl/rv-render ?

Render generator-oriented design artifacts for inspection.

dv/rv-verify ?

Create a verification matrix and smoke-test plan.

ppa/rv-ppa ?

Estimate and compare PPA candidates for the active design.

IO and interfaces ?

Design the contracts between chips

CPU to accelerator?

Define dispatch queues, memory windows, interrupts, telemetry counters, and ownership boundaries.

Peer chip IO?

Capture PCIe/CXL baseline paths and gated VCIX/SSCI candidates with validation expectations.

Memory and cache?

Describe shared L2, HBM paths, cache stashing, IOMMU, coherency, and workload-visible memory behavior.

Debug and RAS?

Keep trace, debug, RAS, security, and safety observability in the interface contract from the beginning.

Chip interconnect ?

Plan from SoC blocks to rack setup

Single package?

Use chiplet or tile links when the design is a tightly coupled compute complex.

Board level?

Use explicit IO contracts when host, accelerator, memory, and management chips sit on a card.

Rack level?

Model telemetry, RAS, power, network, and accelerator dispatch as rack fabric concerns.

Validation gates?

Every interconnect candidate should map to tests, modeled evidence, and a human approval point.