# CHIPS.md

## Product Target

- Name: ACF XM inference control SoC
- Deployment: datacenter inference rack
- Workload: 70B dense LLM inference
- Priority: balanced PPA
- Natural-language intent: Build a RISC-V AI inference control SoC for a 70B-class model-serving rack. Keep latency predictable, reduce watts per token, and use a SiFive XM-style matrix lane with a Linux host-control tier.

## Selected RISC-V Stack

- XM Gen 2: Matrix engine (LLM matrix compute lane with X300 control tiles)
- X300 / X390: ACU and vector control (Companion vector/control path for accelerator orchestration)
- P870-D class host: Linux host-control (Scheduling, telemetry, RAS, virtualization, and rack services)
- Core Designer: Commercial knob validation (Legal configuration packet and design request review)
- Chipyard: Reference SoC flow (Public Chisel-based lane for config, elaboration, and simulation)
- Chisel + CIRCT: Hardware construction (Generator config to FIRRTL/CIRCT lowering and RTL artifacts)

## SiFive and Open Generator Flow

- SiFive validation lane: Core Designer, Freedom Tools/SDK, models, trace/debug, and export review where selected.
- Open reference lane: Chipyard plus Chisel/CIRCT for demo-safe generator config, elaboration, and simulation evidence.
- Toolchain lane: Linux runtime with Freedom Tools and SDK planning

## Constraints

- Rack power cap: 120 kW
- Area budget: 220 mm2
- P99 latency target: 120 ms
- Throughput target: 1,000,000 tokens/sec
- Matrix policy: 128x128 candidate
- Memory plan: shared L2 plus high-bandwidth memory interface

## ACF Prompt

Design ACF XM inference control SoC for datacenter inference rack. The workload is 70B dense LLM inference, and the primary optimization mode is balanced PPA. The user intent is: Build a RISC-V AI inference control SoC for a 70B-class model-serving rack. Keep latency predictable, reduce watts per token, and use a SiFive XM-style matrix lane with a Linux host-control tier.

Use the selected RISC-V stack: XM Gen 2, X300 / X390, P870-D class host, Core Designer, Chipyard, Chisel + CIRCT. Treat SiFive commercial tooling as the validation and productization lane, and use Chipyard with Chisel/CIRCT as the open reference generator lane for demo-safe evidence.

Constrain the proposal to 120 kW rack power, 220 mm2 area pressure, 120 ms p99 latency, and 1,000,000 tokens/sec. Explore a 128x128 candidate matrix policy with shared L2 plus high-bandwidth memory interface.

Produce an approval-gated CHIPS.md, then run the ACF flow from specs to PPA analysis, Chisel RTL synthesis, toolchain planning, DV, emulation, validation testing, qualification, and fab handoff. Mark modeled PPA as modeled evidence, not signoff.

## Execution Plan

1. Specs and source grounding.
2. PPA analysis and Pareto selection.
3. Chipyard render and Chisel RTL synthesis path.
4. SiFive toolchain and software enablement plan.
5. DV test matrix.
6. Emulation smoke run.
7. Validation testing.
8. Qualification package.
9. Fab handoff packet.

## Approval Policy

- Default permission mode: workspace-write.
- Human approval required before CHIPS.md execution, customer export, proprietary IP access, custom ISA acceptance, PPA escalation, and fab handoff.
- Modeled PPA is not signoff evidence.